System Level Testability Issues of Core Based System-on-a-Chip

Testability issues of a core based system-on-a-chip (SOC) are identified and the various solutions available at the different stages of SOC evolution are discussed. It was found that a strategy at core level and system level is needed to achieve first time success of the core based SOC. The issues considered include area, power and delay overheads, Fault coverage, At speed test, Core transparency, Low cost testing techniques, System level test strategies, Low power dissipation during system level test, System level test scheduling and Test generation techniques for Hardware-Software systems. IDDQ testing at core level and system level are discussed and strategies to schedule are discussed. DSM specific testability issues are discussed and their incorporation at core level and system level are planned. A flow for the SOC testability at core and System level is proposed to address the above issues.